[PATCH] D124192: [AMDGPU] Callee must always spill writelane VGPRs

[Nicolai Hähnle via Phabricator via llvm-commits]

nhaehnle added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/SIFrameLowering.cpp:1270-1273
+      if (MI.getOpcode() == AMDGPU::V_WRITELANE_B32)
+        MFI->allocateWWMSpill(MF, MI.getOperand(0).getReg());
+      else if (MI.getOpcode() == AMDGPU::V_READLANE_B32)
+        MFI->allocateWWMSpill(MF, MI.getOperand(1).getReg());
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For V_WRITELANE_B32: Why is this still needed, given that the code calls `allocateWWMSpill` when allocating an SGPR-to-VGPR spill lane?

For V_READLANE_B32: This seems like an unnecessary and unacceptable pessimization. V_READLANE_B32 doesn't modify the register, so there's no need to spill anything of the source register based on it.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D124192/new/

https://reviews.llvm.org/D124192