[PATCH] D136713: [SDAG] avoid vector extract/insert around binop

[Sanjay Patel via Phabricator via llvm-commits]

spatel planned changes to this revision.
spatel marked an inline comment as done.
spatel added inline comments.


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Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:23519
+      TLI.isBinOp(Opcode) && VT.getScalarType() == Scalar.getValueType() &&
+      hasOperation(Opcode, VT)) {
+    // Match an extract element and get a shuffle mask equivalent.
----------------
RKSimon wrote:
> is anything stopping a vectorized integer division with undef elements occurring apart from the fact that almost no target has such an instruction? 
Good point - I don't know how to test it, but we can't do this for opcodes that are not speculatable (because of immediate UB). 

A similar problem came up here:
17dcbd816547 
...so I should've remembered that! :)


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https://reviews.llvm.org/D136713