[PATCH] D136713: [SDAG] avoid vector extract/insert around binop

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


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Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:23519
+      TLI.isBinOp(Opcode) && VT.getScalarType() == Scalar.getValueType() &&
+      hasOperation(Opcode, VT)) {
+    // Match an extract element and get a shuffle mask equivalent.
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is anything stopping a vectorized integer division with undef elements occurring apart from the fact that almost no target has such an instruction? 


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136713/new/

https://reviews.llvm.org/D136713