[PATCH] D136366: [PowerPC] Add new DMR register classes to Future CPU.

[Amy Kwan via Phabricator via llvm-commits]

amyk accepted this revision as: amyk.
amyk added a comment.
This revision is now accepted and ready to land.

I have a couple minor nit comments but I think it overall LGTM.



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Comment at: llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp:367
   }
-
   bool isTLSReg() const { return Kind == TLSRegister; }
----------------
Unrelated space change?


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Comment at: llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td:37
+class XX2Form_AT3_XBp5_P2<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
+                           string asmstr, list<dag> pattern>
+  : I<opcode, OOL, IOL, asmstr, NoItinerary> {
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nit: Align spacing.



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Comment at: llvm/test/CodeGen/PowerPC/future-check-features.ll:1
-; RUN: llc -mattr=pcrelative-memops,prefix-instrs,paired-vector-memops,mma,rop-protect,privileged \
+; RUN: llc -mattr=isa-future-instructions,pcrelative-memops,prefix-instrs,paired-vector-memops,mma,rop-protect,privileged \
 ; RUN:   -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
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nit: Are these run lines too long?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D136366/new/

https://reviews.llvm.org/D136366