[PATCH] D136640: [RISCV][DAG] vslideup/vslidedown with zero offset and undef pass through is a nop

[Philip Reames via Phabricator via llvm-commits]

reames created this revision.
reames added reviewers: craig.topper, asb, kito-cheng, frasercrmck.
Herald added subscribers: sunshaoce, VincentWu, StephenFan, vkmr, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, niosHD, sabuasal, bollu, simoncook, johnrusso, rbar, hiraditya, arichardson, mcrosier.
Herald added a project: All.
reames requested review of this revision.
Herald added subscribers: pcwang-thead, eopXD, MaskRay.
Herald added a project: LLVM.

If we have a vslideup or vslidedown with a zero offset, this is equivalent to copying the active elements into the destination.  If the destination is undefined, then we can ignore masking and VL predication and simply return the source operand.  This may cause additional lanes to be defined, but is otherwise a nop.

Not thought to be important; noticed while glancing at a test diff for something else, and figured I'd knock it out.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D136640

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-bitcast.ll


Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-bitcast.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-bitcast.ll
+++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-bitcast.ll
@@ -201,9 +201,7 @@
 ; RV32-FP-NEXT:    vsetivli zero, 2, e32, m1, ta, ma
 ; RV32-FP-NEXT:    vmv.v.i v8, 0
 ; RV32-FP-NEXT:    vslide1up.vx v9, v8, a1
-; RV32-FP-NEXT:    vslide1up.vx v10, v9, a0
-; RV32-FP-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; RV32-FP-NEXT:    vslideup.vi v8, v10, 0
+; RV32-FP-NEXT:    vslide1up.vx v8, v9, a0
 ; RV32-FP-NEXT:    ret
 ;
 ; RV64-FP-LABEL: bitcast_i64_v4f16:
@@ -221,9 +219,7 @@
 ; RV32-FP-NEXT:    vsetivli zero, 2, e32, m1, ta, ma
 ; RV32-FP-NEXT:    vmv.v.i v8, 0
 ; RV32-FP-NEXT:    vslide1up.vx v9, v8, a1
-; RV32-FP-NEXT:    vslide1up.vx v10, v9, a0
-; RV32-FP-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; RV32-FP-NEXT:    vslideup.vi v8, v10, 0
+; RV32-FP-NEXT:    vslide1up.vx v8, v9, a0
 ; RV32-FP-NEXT:    ret
 ;
 ; RV64-FP-LABEL: bitcast_i64_v2f32:
@@ -241,9 +237,7 @@
 ; RV32-FP-NEXT:    vsetivli zero, 2, e32, m1, ta, ma
 ; RV32-FP-NEXT:    vmv.v.i v8, 0
 ; RV32-FP-NEXT:    vslide1up.vx v9, v8, a1
-; RV32-FP-NEXT:    vslide1up.vx v10, v9, a0
-; RV32-FP-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; RV32-FP-NEXT:    vslideup.vi v8, v10, 0
+; RV32-FP-NEXT:    vslide1up.vx v8, v9, a0
 ; RV32-FP-NEXT:    ret
 ;
 ; RV64-FP-LABEL: bitcast_i64_v1f64:
Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll
+++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll
@@ -510,9 +510,7 @@
 ; RV32-NEXT:    vsetivli zero, 2, e32, m1, ta, ma
 ; RV32-NEXT:    vmv.v.i v8, 0
 ; RV32-NEXT:    vslide1up.vx v9, v8, a1
-; RV32-NEXT:    vslide1up.vx v10, v9, a0
-; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; RV32-NEXT:    vslideup.vi v8, v10, 0
+; RV32-NEXT:    vslide1up.vx v8, v9, a0
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: bitcast_i64_v4i16:
@@ -549,9 +547,7 @@
 ; RV32-NEXT:    vsetivli zero, 2, e32, m1, ta, ma
 ; RV32-NEXT:    vmv.v.i v8, 0
 ; RV32-NEXT:    vslide1up.vx v9, v8, a1
-; RV32-NEXT:    vslide1up.vx v10, v9, a0
-; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; RV32-NEXT:    vslideup.vi v8, v10, 0
+; RV32-NEXT:    vslide1up.vx v8, v9, a0
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: bitcast_i64_v2i32:
@@ -588,9 +584,7 @@
 ; RV32-NEXT:    vsetivli zero, 2, e32, m1, ta, ma
 ; RV32-NEXT:    vmv.v.i v8, 0
 ; RV32-NEXT:    vslide1up.vx v9, v8, a1
-; RV32-NEXT:    vslide1up.vx v10, v9, a0
-; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; RV32-NEXT:    vslideup.vi v8, v10, 0
+; RV32-NEXT:    vslide1up.vx v8, v9, a0
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: bitcast_i64_v1i64:
Index: llvm/lib/Target/RISCV/RISCVISelLowering.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -9883,6 +9883,13 @@
 
     return SDValue();
   }
+  case RISCVISD::VSLIDEDOWN_VL:
+  case RISCVISD::VSLIDEUP_VL:
+    // vslidedown.vi undef, src, 0 -> src
+    // vslideup.vi   undef, src, 0 -> src
+    if (N->getOperand(0).isUndef() && isa<ConstantSDNode>(N->getOperand(2)) &&
+        cast<ConstantSDNode>(N->getOperand(2))->isZero())
+      return N->getOperand(1);
   }
 
   return SDValue();


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D136640.470292.patch
Type: text/x-patch
Size: 3441 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20221024/999406ed/attachment.bin>