[PATCH] D129735: [WIP][RISCV] Add new pass to transform undef to pesudo for vector values.

[Piyou Chen via Phabricator via llvm-commits]

BeMg updated this revision to Diff 469474.
BeMg added a comment.

1. Add sub-register into switch case
2. Update NeedZeroInit into NeedPesudoInit


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D129735/new/

https://reviews.llvm.org/D129735

Files:
  llvm/lib/Target/RISCV/CMakeLists.txt
  llvm/lib/Target/RISCV/RISCV.h
  llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp
  llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
  llvm/test/CodeGen/RISCV/O3-pipeline.ll
  llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll
  llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.ll

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