[PATCH] D129735: [WIP][RISCV] Add new pass to transform undef to pesudo for vector values.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp:167
+  switch (RegClassID) {
+  case RISCV::VRRegClassID:
+  case RISCV::VRNoV0RegClassID:
----------------
This is not maintainable.

I meant something like

```
const TargetRegisterClass *RC = MRI->getRegClass(Reg);
if (RC->hasSuperClassEq(&RISCV::VRRegClass)) {
  Opcode = RISCV::PseudoRVVInitUndefM1;
} else if (RC->hasSuperClassEq(&RRISCV::VRM2RegClass) {
  Opcode = RISCV::PseudoRVVInitUndefM2;
}
...
```


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D129735/new/

https://reviews.llvm.org/D129735