[PATCH] D129735: [WIP][RISCV] Add new pass to transform undef to pesudo for vector values.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

Does this patch work for this test case

  define internal void @foo() {
  loopIR.preheader.i.i:
    %v15 = tail call <vscale x 1 x i16> @llvm.experimental.stepvector.nxv1i16()
    %v17 = tail call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv1i16(<vscale x 8 x i16> poison, <vscale x 1 x i16> %v15, i64 0)
    %vs12.i.i.i = add <vscale x 1 x i16> %v15, shufflevector (<vscale x 1 x i16> insertelement (<vscale x 1 x i16> poison, i16 1, i32 0), <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer)
    %v18 = tail call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv1i16(<vscale x 8 x i16> poison, <vscale x 1 x i16> %vs12.i.i.i, i64 0)
    %vs16.i.i.i = add <vscale x 1 x i16> %v15, shufflevector (<vscale x 1 x i16> insertelement (<vscale x 1 x i16> poison, i16 3, i32 0), <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer)
    %v20 = tail call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv1i16(<vscale x 8 x i16> poison, <vscale x 1 x i16> %vs16.i.i.i, i64 0)
    br label %loopIR3.i.i
  
  loopIR3.i.i:                                      ; preds = %loopIR3.i.i, %loopIR.preheader.i.i
    %v37 = load <vscale x 8 x i8>, ptr addrspace(1) null, align 8
    %v38 = tail call <vscale x 8 x i8> @llvm.riscv.vrgatherei16.vv.nxv8i8.i64(<vscale x 8 x i8> undef, <vscale x 8 x i8> %v37, <vscale x 8 x i16> %v17, i64 4)
    %v40 = tail call <vscale x 8 x i8> @llvm.riscv.vrgatherei16.vv.nxv8i8.i64(<vscale x 8 x i8> undef, <vscale x 8 x i8> %v37, <vscale x 8 x i16> %v18, i64 4)
    %v42 = and <vscale x 8 x i8> %v38, %v40
    %v46 = tail call <vscale x 8 x i8> @llvm.riscv.vrgatherei16.vv.nxv8i8.i64(<vscale x 8 x i8> undef, <vscale x 8 x i8> %v37, <vscale x 8 x i16> %v20, i64 4)
    %v60 = and <vscale x 8 x i8> %v42, %v46
    store <vscale x 8 x i8> %v60, ptr addrspace(1) null, align 4
    br label %loopIR3.i.i
  }
  
  declare <vscale x 1 x i16> @llvm.experimental.stepvector.nxv1i16()
  
  declare <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv1i16(<vscale x 8 x i16>, <vscale x 1 x i16>, i64 immarg) 
  
  declare <vscale x 8 x i8> @llvm.riscv.vrgatherei16.vv.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i16>, i64)


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https://reviews.llvm.org/D129735