[PATCH] D129735: [WIP][RISCV] Add new pass to transform undef to pesudo for vector values.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp:77
+  case RISCV::VRM8RegClassID:
+  case RISCV::VRNoV0RegClassID:
+  case RISCV::VRM2NoV0RegClassID:
----------------
There are a bunch of synthesized register classes. You need to the ID and then ask if that register class is a subclass of the 4 main classes.


================
Comment at: llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp:98
+
+  bool NeedZeroInit = false;
+  SmallVector<MachineOperand *, 1> UserMOs;
----------------
This variable is not named correctly now.


================
Comment at: llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp:135
+  case RISCV::VRNoV0RegClassID:
+    Opcode = RISCV::PseudoRVVInitUndefM1NoV0;
+    break;
----------------
We don't need a pseudo for the NoV0 classes. We need to figure out which main class the register class is a subclass of and use that to pick the pseudo.


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  https://reviews.llvm.org/D129735/new/

https://reviews.llvm.org/D129735