[PATCH] D136235: [AMDGPU][GISel] Constrain selected operands in selectG_BUILD_VECTOR

[Pierre van Houtryve via Phabricator via llvm-commits]

Pierre-vh added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp:692
+                   .addReg(Src0);
+    if (!constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI))
+      return false;
----------------
arsenm wrote:
> Should be able to get away with just src0
Do you mean calling constrainOperandRegClass directly?
If possible I'd rather keep `constrainSelectedInstRegOperands`. We're doing the same operation in both cases (we want the operands to be constrained to the instruction's desired RB) and I feel like it's easier to follow if we just use the same function in both cases


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  https://reviews.llvm.org/D136235/new/

https://reviews.llvm.org/D136235