[PATCH] D136081: [DAG] Fold (sra (or (shl x, c1), (shl y, c2)), c1) -> (sext_inreg (or x, (shl y,c2-c1)) iff c2 >= c1

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:9459-9460
+    if (N00C && N01C &&
+        N00C->getAPIntValue().uge(N1C->getZExtValue()) &&
+        N01C->getAPIntValue().uge(N1C->getZExtValue())) {
+      unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue();
----------------
foad wrote:
> Seems like an odd mix of getAPIntValue vs getZExtValue.
Yeah, its to account for the fact that the inner shift amount types might not match N1 (or might be out of bounds) - its messy I agree but adding all the type/inrange matching was worse :( 


================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:9467
+      if (!LegalOperations ||
+          TLI.getOperationAction(ISD::SIGN_EXTEND_INREG, ExtVT) ==
+              TargetLowering::Legal) {
----------------
foad wrote:
> How does this work? Is it checking legality of SIGN_EXTEND_INREG with the specified inner type, irrespective of the outer type?
This was copied from the  (sra (shl x, c1), c1) -> sext_inreg fold immediately above - I'll see if I can improve it.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136081/new/

https://reviews.llvm.org/D136081