[PATCH] D136081: [DAG] Fold (sra (or (shl x, c1), (shl y, c2)), c1) -> (sext_inreg (or x, (shl y,c2-c1)) iff c2 >= c1

[Jay Foad via Phabricator via llvm-commits]

foad added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:9459-9460
+    if (N00C && N01C &&
+        N00C->getAPIntValue().uge(N1C->getZExtValue()) &&
+        N01C->getAPIntValue().uge(N1C->getZExtValue())) {
+      unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue();
----------------
Seems like an odd mix of getAPIntValue vs getZExtValue.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:9467
+      if (!LegalOperations ||
+          TLI.getOperationAction(ISD::SIGN_EXTEND_INREG, ExtVT) ==
+              TargetLowering::Legal) {
----------------
How does this work? Is it checking legality of SIGN_EXTEND_INREG with the specified inner type, irrespective of the outer type?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136081/new/

https://reviews.llvm.org/D136081