[PATCH] D136081: [DAG] Fold (sra (or (shl x, c1), (shl y, c2)), c1) -> (sext_inreg (or x, (shl y,c2-c1)) iff c2 >= c1

Jay Foad via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Oct 18 07:28:35 PDT 2022


foad accepted this revision.
foad added a comment.
This revision is now accepted and ready to land.

LGTM either with or without improving the legality check for SIGN_EXTEND_INREG.



================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:9459-9460
+    if (N00C && N01C &&
+        N00C->getAPIntValue().uge(N1C->getZExtValue()) &&
+        N01C->getAPIntValue().uge(N1C->getZExtValue())) {
+      unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue();
----------------
RKSimon wrote:
> foad wrote:
> > Seems like an odd mix of getAPIntValue vs getZExtValue.
> Yeah, its to account for the fact that the inner shift amount types might not match N1 (or might be out of bounds) - its messy I agree but adding all the type/inrange matching was worse :( 
Oh I see. I guess using getZExtValue in both places would have been less surprising.


Repository:
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CHANGES SINCE LAST ACTION
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https://reviews.llvm.org/D136081



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