[PATCH] D136081: [DAG] Fold (sra (or (shl x, c1), (shl y, c2)), c1) -> (sext_inreg (or x, (shl y,c2-c1)) iff c2 >= c1

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon created this revision.
RKSimon added reviewers: foad, spatel.
Herald added subscribers: kosarev, ecnelises, kerbowa, hiraditya, tpr, jvesely.
Herald added a project: All.
RKSimon requested review of this revision.
Herald added a project: LLVM.

Addresses the AMDGPU regression identified in D136042 <https://reviews.llvm.org/D136042> where we were losing signed BFE patterns after sinking shifts behind logic ops.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D136081

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/test/CodeGen/AMDGPU/bfe-patterns.ll

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