[PATCH] D135794: [RISCV] Use vslide1up for inserting bottom element into splat vector

[Philip Reames via Phabricator via llvm-commits]

reames added a comment.

In D135794#3854627 <https://reviews.llvm.org/D135794#3854627>, @craig.topper wrote:

> The slide1up may be more expensive than vmv.s.x as LMUL increases. The upper elements will get shifted even though they are all the same. Despite vmv.s.x having an LMUL typed result in SelectionDAG and MachineIR it only reads and writes one LMUL==1 vector register.

Had not considered this point.  Would it be reasonable to restrict this to LMUL1 types?



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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:9735
+    // mismatch.  Can also allow a source vector with a larger VL.
+    if (SrcVec.getOpcode() == RISCVISD::VMV_V_X_VL &&
+        SrcVec.getSimpleValueType() == VT && SrcVec.getOperand(2) == VL) {
----------------
craig.topper wrote:
> reames wrote:
> > Noticed when glancing through other code that I hadn't handled the vmv.v.i case here.  Consider that added to the todo list above.  
> There is no VMV_V_I_VL. So doesn't this already handle vmv.v.i?
Well, empirically no.  I see examples of vmv.v.i patterns which would match this conceptually, but aren't being caught by this one.  Haven't looked into why yet.  


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  https://reviews.llvm.org/D135794/new/

https://reviews.llvm.org/D135794