[PATCH] D135794: [RISCV] Use vslide1up for inserting bottom element into splat vector

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

In D135794#3855633 <https://reviews.llvm.org/D135794#3855633>, @reames wrote:

> In D135794#3854627 <https://reviews.llvm.org/D135794#3854627>, @craig.topper wrote:
>
>> The slide1up may be more expensive than vmv.s.x as LMUL increases. The upper elements will get shifted even though they are all the same. Despite vmv.s.x having an LMUL typed result in SelectionDAG and MachineIR it only reads and writes one LMUL==1 vector register.
>
> Had not considered this point.  Would it be reasonable to restrict this to LMUL1 types?

I think that's going to depend on the microarchitecture. If the ALU width is less than VLEN bits, a vslide1up could still require more ALU cycles than vmv.s.x.

The cases that replace a vmv and a vmv.s.x are interesting. On an architecture without renaming or move elimination, the vmv might be considered an ALU op.


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