[PATCH] D135794: [RISCV] Use vslide1up for inserting bottom element into splat vector

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

The slide1up may be more expensive than vmv.s.x as LMUL increases. The upper elements will get shifted even though they are all the same. Despite vmv.s.x having an LMUL typed result in SelectionDAG and MachineIR it only reads and writes one LMUL==1 vector register.



================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:9735
+    // mismatch.  Can also allow a source vector with a larger VL.
+    if (SrcVec.getOpcode() == RISCVISD::VMV_V_X_VL &&
+        SrcVec.getSimpleValueType() == VT && SrcVec.getOperand(2) == VL) {
----------------
reames wrote:
> Noticed when glancing through other code that I hadn't handled the vmv.v.i case here.  Consider that added to the todo list above.  
There is no VMV_V_I_VL. So doesn't this already handle vmv.v.i?


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:9736
+    if (SrcVec.getOpcode() == RISCVISD::VMV_V_X_VL &&
+        SrcVec.getSimpleValueType() == VT && SrcVec.getOperand(2) == VL) {
+      return DAG.getNode(RISCVISD::VSLIDE1UP_VL, DL, VT, DAG.getUNDEF(VT),
----------------
I think the VT match is guaranteed by the rules we have defined for RISCVISD::VSLIDE1UP_VL.

```
def SDTRVVSlide1 : SDTypeProfile<1, 5, [                                         
  SDTCisVec<0>, SDTCisSameAs<1, 0>, SDTCisSameAs<2, 0>, SDTCisInt<0>,            
  SDTCisVT<3, XLenVT>, SDTCVecEltisVT<4, i1>, SDTCisSameNumEltsAs<0, 4>,         
  SDTCisVT<5, XLenVT>                                                            
]>;
```


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D135794/new/

https://reviews.llvm.org/D135794