[PATCH] D135807: [WIP][RISCV][InsertVSETVLI] Allow promotion of TA to TU and MA to MU

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll:527
+; RV32ELEN32-NEXT:    vsetivli zero, 2, e32, m1, tu, ma
 ; RV32ELEN32-NEXT:    vmv.v.x v8, a1
 ; RV32ELEN32-NEXT:    vmv.s.x v8, a0
----------------
So now we can't execute this instruction until the previous writer of vmv.v.x completes? At least on a renamed microarchitecture.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D135807/new/

https://reviews.llvm.org/D135807