[PATCH] D135807: [WIP][RISCV][InsertVSETVLI] Allow promotion of TA to TU and MA to MU

[Philip Reames via Phabricator via llvm-commits]

reames added inline comments.


================
Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll:527
+; RV32ELEN32-NEXT:    vsetivli zero, 2, e32, m1, tu, ma
 ; RV32ELEN32-NEXT:    vmv.v.x v8, a1
 ; RV32ELEN32-NEXT:    vmv.s.x v8, a0
----------------
craig.topper wrote:
> So now we can't execute this instruction until the previous writer of vmv.v.x completes? At least on a renamed microarchitecture.
For the instruction "vmv.v.x v8, a1", there's now a false dependence on the prior value of v8.  Previously, the hardware could ignore this dependence as the input value could be ignored, and the high lanes unconditionally set to -1.  After the change to TU, the hardware must wait for the dependency to be resolved.  


Repository:
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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D135807/new/

https://reviews.llvm.org/D135807