[PATCH] D135541: [TargetLowering][RISCV][X86] Support even divisors in expandDIVREMByConstant.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:7256
+                      DAG.getShiftAmountConstant(HBitWidth - TrailingZeros,
+                                                 HiLoVT, dl)));
+      ShiftedLH = DAG.getNode(ISD::SRL, dl, HiLoVT, ShiftedLH,
----------------
RKSimon wrote:
> Would we benefit at all from creating a ISD::FSHL node here?
We don't use FSHL/FSHR in ExpandShiftByConstant so I think we should be ok. Looks like DAGCombiner is matching it to FSHL for X86.


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  https://reviews.llvm.org/D135541/new/

https://reviews.llvm.org/D135541