[PATCH] D135541: [TargetLowering][RISCV][X86] Support even divisors in expandDIVREMByConstant.

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:7256
+                      DAG.getShiftAmountConstant(HBitWidth - TrailingZeros,
+                                                 HiLoVT, dl)));
+      ShiftedLH = DAG.getNode(ISD::SRL, dl, HiLoVT, ShiftedLH,
----------------
Would we benefit at all from creating a ISD::FSHL node here?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D135541/new/

https://reviews.llvm.org/D135541