[PATCH] D135418: [VP][RISCV] Add vp.smax/smin/umax/umin intrinsics

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp:175
 
+  case ISD::VP_UMIN:
+  case ISD::VP_UMAX:
----------------
frasercrmck wrote:
> I note that we call `PromoteIntRes_UMINUMAX` for regular UMIN/UMAX. Is there something there that we want to do for the VP versions too?
I think that uses sext for scalar i32 on RISC-V by calling isSExtCheaperThanZExt


Repository:
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  https://reviews.llvm.org/D135418/new/

https://reviews.llvm.org/D135418