[PATCH] D135302: [AArch64] Support SETCCCARRY lowering

[Filipp Zhinkin via Phabricator via llvm-commits]

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Updated tests



================
Comment at: llvm/test/CodeGen/AArch64/i128-cmp.ll:24
 ; CHECK-NEXT:    eor x9, x0, x2
 ; CHECK-NEXT:    orr x8, x9, x8
 ; CHECK-NEXT:    cmp x8, #0
----------------
Also checking if it's possible to use setcccarry to lower setcc eq/ne. It seems like it may improve code on x86, ARM and AArch64, but I'd prefer fixing it separately.


Support SETCCCARRY lowering to SBCS instruction.

Related issue: https://github.com/llvm/llvm-project/issues/44629


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D135302

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/test/CodeGen/AArch64/arm64-atomic-128.ll
  llvm/test/CodeGen/AArch64/fpclamptosat.ll
  llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll
  llvm/test/CodeGen/AArch64/i128-cmp.ll

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