[PATCH] D135302: [AArch64] Support SETCCCARRY lowering

[Eli Friedman via Phabricator via llvm-commits]

efriedma added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:417
   setOperationAction(ISD::JumpTable, MVT::i64, Custom);
+  setOperationAction(ISD::SETCCCARRY, MVT::i32, Custom);
+  setOperationAction(ISD::SETCCCARRY, MVT::i64, Custom);
----------------
Do we ever actually use SETCCCARRY for i32 on targets where i64 is legal?


================
Comment at: llvm/test/CodeGen/AArch64/i128-cmp.ll:24
 ; CHECK-NEXT:    eor x9, x0, x2
 ; CHECK-NEXT:    orr x8, x9, x8
 ; CHECK-NEXT:    cmp x8, #0
----------------
fzhinkin wrote:
> Also checking if it's possible to use setcccarry to lower setcc eq/ne. It seems like it may improve code on x86, ARM and AArch64, but I'd prefer fixing it separately.
Not sure how you could use setcccarry for equality; the carry bit doesn't contain enough information.  You need something more like the AArch64 ccmp.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D135302/new/

https://reviews.llvm.org/D135302