[llvm] 3ec0085 - [DAG] Update `isKnownNeverNaN` for `FMA/FMAD`

[Pierre van Houtryve via llvm-commits]

Author: Pierre van Houtryve
Date: 2022-10-06T06:52:36Z
New Revision: 3ec0085c3fd4218f776a4318e563a8fe73f01778

URL: https://github.com/llvm/llvm-project/commit/3ec0085c3fd4218f776a4318e563a8fe73f01778
DIFF: https://github.com/llvm/llvm-project/commit/3ec0085c3fd4218f776a4318e563a8fe73f01778.diff

LOG: [DAG] Update `isKnownNeverNaN` for `FMA/FMAD`

We can still get a NaN even if none of the operands are NaN,
e.g. from +inf/-inf. D50804 didn't catch that.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D134854

Added: 
    

Modified: 
    llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    llvm/test/CodeGen/AMDGPU/known-never-nan.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 80703066d5f0..ce4aeeea4ebc 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -4692,7 +4692,9 @@ bool SelectionDAG::isKnownNeverNaN(SDValue Op, bool SNaN, unsigned Depth) const
   case ISD::FDIV:
   case ISD::FREM:
   case ISD::FSIN:
-  case ISD::FCOS: {
+  case ISD::FCOS:
+  case ISD::FMA:
+  case ISD::FMAD: {
     if (SNaN)
       return true;
     // TODO: Need isKnownNeverInfinity
@@ -4729,14 +4731,6 @@ bool SelectionDAG::isKnownNeverNaN(SDValue Op, bool SNaN, unsigned Depth) const
   case ISD::SINT_TO_FP:
   case ISD::UINT_TO_FP:
     return true;
-  case ISD::FMA:
-  case ISD::FMAD: {
-    if (SNaN)
-      return true;
-    return isKnownNeverNaN(Op.getOperand(0), SNaN, Depth + 1) &&
-           isKnownNeverNaN(Op.getOperand(1), SNaN, Depth + 1) &&
-           isKnownNeverNaN(Op.getOperand(2), SNaN, Depth + 1);
-  }
   case ISD::FSQRT: // Need is known positive
   case ISD::FLOG:
   case ISD::FLOG2:

diff  --git a/llvm/test/CodeGen/AMDGPU/known-never-nan.ll b/llvm/test/CodeGen/AMDGPU/known-never-nan.ll
index 567208e4c816..0a9bfbbf99cd 100644
--- a/llvm/test/CodeGen/AMDGPU/known-never-nan.ll
+++ b/llvm/test/CodeGen/AMDGPU/known-never-nan.ll
@@ -1,17 +1,18 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck %s
 
 define half @known_nnan_extract_vector_elt(float %a, float %b, i32 %idx, half %c) {
-; GCN-LABEL: known_nnan_extract_vector_elt:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_cvt_pkrtz_f16_f32 v0, v0, v1
-; GCN-NEXT:    v_lshlrev_b32_e32 v1, 4, v2
-; GCN-NEXT:    v_lshrrev_b32_e32 v0, v1, v0
-; GCN-NEXT:    v_add_f16_e32 v1, 1.0, v3
-; GCN-NEXT:    v_cmp_lt_f16_e32 vcc, v0, v1
-; GCN-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; CHECK-LABEL: known_nnan_extract_vector_elt:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    s_waitcnt_vscnt null, 0x0
+; CHECK-NEXT:    v_cvt_pkrtz_f16_f32_e32 v0, v0, v1
+; CHECK-NEXT:    v_lshlrev_b32_e32 v1, 4, v2
+; CHECK-NEXT:    v_add_f16_e32 v2, 1.0, v3
+; CHECK-NEXT:    v_lshrrev_b32_e32 v0, v1, v0
+; CHECK-NEXT:    v_cmp_lt_f16_e32 vcc_lo, v0, v2
+; CHECK-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %cvt = call nnan <2 x half> @llvm.amdgcn.cvt.pkrtz(float %a, float %b)
   %extract = extractelement <2 x half> %cvt, i32 %idx
   %canon = call half @llvm.canonicalize.f16(half %extract)
@@ -21,5 +22,31 @@ define half @known_nnan_extract_vector_elt(float %a, float %b, i32 %idx, half %c
   ret half %select
 }
 
-declare <2 x half> @llvm.amdgcn.cvt.pkrtz(float, float) #0
-declare half @llvm.canonicalize.f16(half) #0
+; should not emit v_max
+define float @fma_not_fmaxnm_maybe_nan(i32 %i1, i32 %i2, i32 %i3) #0 {
+; CHECK-LABEL: fma_not_fmaxnm_maybe_nan:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    s_waitcnt_vscnt null, 0x0
+; CHECK-NEXT:    v_cvt_f32_u32_e32 v0, v0
+; CHECK-NEXT:    v_cvt_f32_u32_e32 v1, v1
+; CHECK-NEXT:    v_fmaak_f32 v0, v1, v0, 0xff800000
+; CHECK-NEXT:    v_cmp_nge_f32_e32 vcc_lo, 0xff800000, v0
+; CHECK-NEXT:    v_cndmask_b32_e32 v0, 0xff800000, v0, vcc_lo
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+  %f1 = uitofp i32 %i1 to float
+  %f2 = uitofp i32 %i2 to float
+  %f3 = uitofp i32 %i2 to float
+  %fma = tail call float @llvm.fma.f32(float %f2, float %f1, float 0xfff0000000000000)
+  %cmp = fcmp ugt float %fma, 0xfff0000000000000
+  %val = select i1 %cmp, float %fma, float 0xfff0000000000000
+  ret float %val
+}
+
+declare float @llvm.fma.f32(float, float, float) nounwind readnone
+declare float @llvm.amdgcn.fmad.ftz.f32(float, float, float)
+
+declare <2 x half> @llvm.amdgcn.cvt.pkrtz(float, float)
+declare half @llvm.canonicalize.f16(half)
+
+attributes #0 = { nounwind "no-signed-zeros-fp-math"="true" "target-features"="+mad-mac-f32-insts" }