[PATCH] D134893: [LSR][TTI][RISCV] Add isAllowTerminatingConditionFoldingAfterLSR into TTI and enable it for RISC-V

[Yueh-Ting (eop) Chen via Phabricator via llvm-commits]

eopXD added a comment.

I ran through lit test under `llvm/test/CodeGen/RISCV`, these two affected test case shows benefit of the transformation.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D134893/new/

https://reviews.llvm.org/D134893