[llvm] 4c4e544 - [ARM] Add an option for disabling omitting DLS.

[David Green via llvm-commits]

Author: David Green
Date: 2022-09-29T17:42:45+01:00
New Revision: 4c4e544cd8fc1da610bf69ee6524e88a8401cdba

URL: https://github.com/llvm/llvm-project/commit/4c4e544cd8fc1da610bf69ee6524e88a8401cdba
DIFF: https://github.com/llvm/llvm-project/commit/4c4e544cd8fc1da610bf69ee6524e88a8401cdba.diff

LOG: [ARM] Add an option for disabling omitting DLS.

Useful for testing, this option disables when `DLS lr, lr` gets removed.

Added: 
    

Modified: 
    llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp b/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
index 7abde69be25a2..3c81b19fd1779 100644
--- a/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
+++ b/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
@@ -81,6 +81,11 @@ DisableTailPredication("arm-loloops-disable-tailpred", cl::Hidden,
     cl::desc("Disable tail-predication in the ARM LowOverheadLoop pass"),
     cl::init(false));
 
+static cl::opt<bool>
+    DisableOmitDLS("arm-disable-omit-dls", cl::Hidden,
+                   cl::desc("Disable omitting 'dls lr, lr' instructions"),
+                   cl::init(false));
+
 static bool isVectorPredicated(MachineInstr *MI) {
   int PIdx = llvm::findFirstVPTPredOperandIdx(*MI);
   return PIdx != -1 && MI->getOperand(PIdx + 1).getReg() == ARM::VPR;
@@ -1553,7 +1558,8 @@ MachineInstr* ARMLowOverheadLoops::ExpandLoopStart(LowOverheadLoop &LoLoop) {
 
   // A DLS lr, lr we needn't emit
   MachineInstr* NewStart;
-  if (Opc == ARM::t2DLS && Count.isReg() && Count.getReg() == ARM::LR) {
+  if (!DisableOmitDLS && Opc == ARM::t2DLS && Count.isReg() &&
+      Count.getReg() == ARM::LR) {
     LLVM_DEBUG(dbgs() << "ARM Loops: Didn't insert start: DLS lr, lr");
     NewStart = nullptr;
   } else {