[PATCH] D134893: [LSR][TTI][RISCV] Add isAllowTerminatingConditionFoldingAfterLSR into TTI and enable it for RISC-V

[Yueh-Ting (eop) Chen via Phabricator via llvm-commits]

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Previously in D132443 <https://reviews.llvm.org/D132443>, the transformation was added and guarded by an option.
This commit attempts to create an TTI and enable it for the RISC-V backend.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D134893

Files:
  llvm/include/llvm/Analysis/TargetTransformInfo.h
  llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
  llvm/include/llvm/CodeGen/BasicTTIImpl.h
  llvm/lib/Analysis/TargetTransformInfo.cpp
  llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
  llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
  llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
  llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store-asm.ll
  llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll

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