[PATCH] D134892: [X86] Avoid miscompile in combineOr (X86ISelLowering.cpp)

[Bjorn Pettersson via Phabricator via llvm-commits]

bjope added a comment.

For the record, we found this problem after having merged

  commit d1baed7c9c8341c43c696cce1b7ec846c21b0b45
  Author: Amaury Séchet <deadalnix at gmail.com>
  Date:   Fri Aug 5 13:33:07 2022 +0000
  
      [DAG] select Cond, -1, C --> or (sext Cond), C if Cond is MVT::i1
      
      This seems to be beneficial overall, except for midpoint-int.ll .
      
      The X86 backend seems to generate zeroing that are not necesary.
      
      Reviewed By: shchenz
      
      Differential Revision: https://reviews.llvm.org/D131260

even though the bug seems to have been around since Aug 7 (commit 9bceb8981d32fe <https://reviews.llvm.org/rG9bceb8981d32fe9465257c31413395f445ab05d8>).


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  https://reviews.llvm.org/D134892/new/

https://reviews.llvm.org/D134892