[PATCH] D134711: [AArch64] Select SMULL for zero extended vectors when top bit is zero

[Zain Jaffal via Phabricator via llvm-commits]

zjaffal updated this revision to Diff 463823.
zjaffal added a comment.

Refactor common code for selecting multiplication instruction out of the main code for `LowerMul`, rewrite checking for the top bit to use `DAG.SignBitIsZero` and refactor on top of the added new tests


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D134711/new/

https://reviews.llvm.org/D134711

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/aarch64-smull.ll

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