[PATCH] D134711: [AArch64] Select SMULL for zero extended vectors when top bit is zero

[Florian Hahn via Phabricator via llvm-commits]

fhahn added a comment.

Thanks for the update! Could you split out the code that adds `selectUmullSmull` into a separate NFC patch and then update this patch to just add the new handling for converting zext to sext?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D134711/new/

https://reviews.llvm.org/D134711