[PATCH] D134711: [AArch64] Select SMULL for zero extended vectors when top bit is zero

[Zain Jaffal via Phabricator via llvm-commits]

zjaffal added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:4405
+      unsigned PreZextSizeInBits = ZextOperand.getScalarValueSizeInBits();
+      KnownBits Bits = DAG.computeKnownBits(ZextOperand, 4);
+      KnownBits LastBitValue = Bits.extractBits(1, PreZextSizeInBits - 1);
----------------
spatel wrote:
> Just a couple of drive-by comments:
> 1. Why is this passing depth 4?
> 2. Use DAG.SignBitIsZero() to make this easier to read? ("last bit" usually means the LSB, not the MSB/signbit).
The depth is 4 following a similar code block in the same file 
```
// Check if the value is zero-extended from i1 to i8
static bool checkZExtBool(SDValue Arg, const SelectionDAG &DAG) {
  unsigned SizeInBits = Arg.getValueType().getSizeInBits();
  if (SizeInBits < 8)
    return false;

  APInt RequredZero(SizeInBits, 0xFE);
  KnownBits Bits = DAG.computeKnownBits(Arg, 4);
  bool ZExtBool = (Bits.Zero & RequredZero) == RequredZero;
  return ZExtBool;
}
```
I tested the implementation using `DAG.SignBitIsZero()` and it works with `depth=0` 


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  https://reviews.llvm.org/D134711/new/

https://reviews.llvm.org/D134711