[PATCH] D134711: [AArch64] Select SMULL for zero extended vectors when top bit is zero

[Sanjay Patel via Phabricator via llvm-commits]

spatel added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:4405
+      unsigned PreZextSizeInBits = ZextOperand.getScalarValueSizeInBits();
+      KnownBits Bits = DAG.computeKnownBits(ZextOperand, 4);
+      KnownBits LastBitValue = Bits.extractBits(1, PreZextSizeInBits - 1);
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Just a couple of drive-by comments:
1. Why is this passing depth 4?
2. Use DAG.SignBitIsZero() to make this easier to read? ("last bit" usually means the LSB, not the MSB/signbit).


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D134711/new/

https://reviews.llvm.org/D134711