[PATCH] D134851: [RISCV][WIP] Enable the local stack allocation pass for RISC-V.

[Jessica Clarke via Phabricator via llvm-commits]

jrtc27 added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.h:77
+  bool isStackIdSafeForLocalArea(unsigned StackId) const override {
+    // We don't support putting SVE objects into the pre-allocated local
+    // frame block at the moment.
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Bit too Arm-flavoured :)


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Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp:390-395
+  int64_t FPOffset = Offset - (Subtarget.is64Bit() ? 104 : 52);
+  // Consider FS0-FS11 if present.
+  if (Subtarget.hasStdExtD())
+    FPOffset -= 96;
+  else if (Subtarget.hasStdExtF())
+    FPOffset -= 48;
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These should at least be based on XLEN and FLEN calculations rather than a bunch of hard-coded constants, but can they be calculated purely based on the ABI's callee saved register sets?

Also shouldn't the D/F checks be ABI-based rather than ISA-based? They're all caller-saved in the soft-float ABI, and similarly for the high parts of wider-than-ABI_FLEN registers.


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Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp:404
+  // FIXME: This is a total SWAG number. We should run some statistics
+  //        and pick a real one.
+  Offset += 128; // 128 bytes of spill slots
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Maybe also fudged by XLEN?


Repository:
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  https://reviews.llvm.org/D134851/new/

https://reviews.llvm.org/D134851