[PATCH] D134851: [RISCV][WIP] Enable the local stack allocation pass for RISC-V.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added reviewers: reames, asb, frasercrmck, kito-cheng, luismarques.
Herald added subscribers: sunshaoce, VincentWu, StephenFan, vkmr, evandro, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, niosHD, sabuasal, simoncook, johnrusso, rbar, hiraditya, kristof.beyls, arichardson.
Herald added a project: All.
craig.topper requested review of this revision.
Herald added subscribers: pcwang-thead, eopXD, MaskRay.
Herald added a project: LLVM.

While investigating PR58027, I noticed that ARM and AArch64 use
this pass. It creates a virtual base register for the stack accesses
and prevents an emergency spill slot from being needed.

I've done no testing of this other than PR58027. No lit tests were
affected.

Does this patch seem like something we should pursue?


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D134851

Files:
  llvm/lib/Target/RISCV/RISCVFrameLowering.h
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.h

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D134851.463756.patch
Type: text/x-patch
Size: 7529 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20220929/a6cfaedf/attachment.bin>