[PATCH] D134851: [RISCV][WIP] Enable the local stack allocation pass for RISC-V.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp:390-395
+  int64_t FPOffset = Offset - (Subtarget.is64Bit() ? 104 : 52);
+  // Consider FS0-FS11 if present.
+  if (Subtarget.hasStdExtD())
+    FPOffset -= 96;
+  else if (Subtarget.hasStdExtF())
+    FPOffset -= 48;
----------------
jrtc27 wrote:
> These should at least be based on XLEN and FLEN calculations rather than a bunch of hard-coded constants, but can they be calculated purely based on the ABI's callee saved register sets?
> 
> Also shouldn't the D/F checks be ABI-based rather than ISA-based? They're all caller-saved in the soft-float ABI, and similarly for the high parts of wider-than-ABI_FLEN registers.
Thanks I had never looked into the specifics of the soft float ABI.

I'll definitely look into improving this code if we think it's worthwhile to enable this pass.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D134851/new/

https://reviews.llvm.org/D134851