[PATCH] D134621: [RISCV][WIP] Teach SExtWRemoval to recognize sign extended values that come from arguments.

[Philip Reames via Phabricator via llvm-commits]

reames added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:10566
 
+  // If input is sign extended from 32 bits, note it for the SExtWRemoval pass.
+  if (In.isOrigArg()) {
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One thought here.

If this logic is sound, then we could use a similar approach to prove known bits for the RegisterSDNode representing the argument location.  This would allow SDAG to eliminate some extends, but more importantly, might allow us to do this in a place more likely to expose any unsoundness in a way it gets caught.  Particularly, if we can do that in target independent code.  

Looking at the calling code, I think this basically translates to putting an AssertSext after the CopyFromReg?  Actually, it looks like the caller already does this for us based on the isZExt and isSExt flags.

I suspect you can rewrite this code as if not split and is sext from the flags.  Not sure mind you, just suspect.  


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D134621/new/

https://reviews.llvm.org/D134621