[PATCH] D134621: [RISCV][WIP] Teach SExtWRemoval to recognize sign extended values that come from arguments.

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:10568-10572
+    Argument *OrigArg = MF.getFunction().getArg(In.getOrigArgIndex());
+    if (OrigArg->getType()->isIntegerTy()) {
+      unsigned BitWidth = OrigArg->getType()->getIntegerBitWidth();
+      // An input zero extended from i31 can also be considered sign extended.
+      if ((BitWidth <= 32 && In.Flags.isSExt()) ||
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Don't see why you need to look at the underlying IR here instead of just relying on the argument flags


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Comment at: llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp:9
 //
 // This pass removes unneeded sext.w instructions at the MI level.
 //
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It feels wrong to me that you would need to optimize these after selection but I guess I don't know why you are seeing these


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D134621/new/

https://reviews.llvm.org/D134621