[PATCH] D134711: [AArch64] Select SMULL for zero extended vectors when top bit is zero

[Florian Hahn via Phabricator via llvm-commits]

fhahn added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:4418
+    // Capture UMULL optimizations if SMULL wasn't selected
+    if (!NewOpc) {
+      if (isN0ZExt && isN1ZExt)
----------------
The logic with the nested `ifs` is a bit hard to follow now.

Would it be possible to simplify the code by moving all those checks to a static helper function which returns the new opcode (and updates the other variables as required)? This would allow to use early exits to reduce the need for nested of conditions.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D134711/new/

https://reviews.llvm.org/D134711