[PATCH] D134711: [AArch64] Select SMULL for zero extended vectors when top bit is zero
Florian Hahn via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 28 05:30:10 PDT 2022
fhahn added inline comments.
================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:4418
+ // Capture UMULL optimizations if SMULL wasn't selected
+ if (!NewOpc) {
+ if (isN0ZExt && isN1ZExt)
----------------
The logic with the nested `ifs` is a bit hard to follow now.
Would it be possible to simplify the code by moving all those checks to a static helper function which returns the new opcode (and updates the other variables as required)? This would allow to use early exits to reduce the need for nested of conditions.
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rG LLVM Github Monorepo
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https://reviews.llvm.org/D134711/new/
https://reviews.llvm.org/D134711
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