[PATCH] D134711: [AArch64] Select SMULL for zero extended vectors when top bit is zero

[Hsiangkai Wang via Phabricator via llvm-commits]

HsiangKai added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:4416
+      }
+    } else if (isN0ZExt && isN1ZExt)
       NewOpc = AArch64ISD::UMULL;
----------------
NewOpc has no value if LastBitValue is not zero in the previous if block. It will lost some opportunities to use UMULL to do unsigned multiplication. It is why some test cases become worse.

Do you think it is a good way to check NewOpc before checking `isN0ZExt && isN1ZExt`? That is

```
if (!NewOpc) {
  if (isN0ZExt && isN1ZExt)
    NewOpc = AArch64ISD::UMULL;
  else if (isN1SExt || isN1ZExt) {
    // ...
  }
}
```


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D134711/new/

https://reviews.llvm.org/D134711