[PATCH] D134711: [AArch64] Select SMULL for zero extended vectors when top bit is zero

[Zain Jaffal via Phabricator via llvm-commits]

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we can safely replace a `zext` instruction with `sext` if the top bit is zero. This is useful because we can select `smull` when both operands are sign extended.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D134711

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/aarch64-smull.ll

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