[PATCH] D134711: [AArch64] Select SMULL for zero extended vectors when top bit is zero

[Florian Hahn via Phabricator via llvm-commits]

fhahn requested changes to this revision.
fhahn added a comment.
This revision now requires changes to proceed.

Thanks for the patch @zjaffal! Please update the code as suggested by @HsiangKai  to fix the regressions in the test case.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D134711/new/

https://reviews.llvm.org/D134711