[PATCH] D133808: [RISCV][InsertVSETVLI] Operations with no tail elements are tail agnostic

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp:833
       int64_t Imm = VLOp.getImm();
       // Conver the VLMax sentintel to X0 register.
+      if (Imm == RISCV::VLMaxSentinel) {
----------------
Can fix the spelling of "sentinel" while you're here?


================
Comment at: llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp:837
+        // No tail elements --> tail agnostic.  Note that vmv.s.x and
+        // vmv.s.f define tail elements differently, and thus VL=VLMAX
+        // does not imply tail agnostic for those.
----------------
vmv.s.f -> vfmv.s.f


================
Comment at: llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp:840
+        // TODO: move this to e.g. a dag combine?
+        TailAgnostic |= !isScalarMoveInstr(MI);
+      } else
----------------
reductions and vcompress also define tail elements differently.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D133808/new/

https://reviews.llvm.org/D133808