[PATCH] D133808: [RISCV][InsertVSETVLI] Operations with no tail elements are tail agnostic

[Philip Reames via Phabricator via llvm-commits]

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Most vector instructions define tail elements at those being past VL.  (vmv.s.f and vmv.s.x are defined differently.)  When VL==VLMAX, there are no tail elements, so tail agnostic and tail undisturbed are equivalent.  Canonicalize to TA as that gives us more flexibility.

Honestly, this should really be done earlier, but then we'd need to have policy flags on all the psuedos.  I started down that path, and then decided this was radically simpler.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D133808

Files:
  llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
  llvm/test/CodeGen/RISCV/rvv/vector-splice.ll
  llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir

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