[PATCH] D133808: [RISCV][InsertVSETVLI] Operations with no tail elements are tail agnostic
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Sep 13 19:04:04 PDT 2022
craig.topper added inline comments.
================
Comment at: llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp:840
+ // TODO: move this to e.g. a dag combine?
+ TailAgnostic |= !isScalarMoveInstr(MI);
+ } else
----------------
craig.topper wrote:
> reductions and vcompress also define tail elements differently.
I'm also not sure how this interacts with the tail elements past VLMAX in a register for fractional LMUL. Tail undisturbed policy is documented as preserving them.
I'm not sure if its possible to control what value is in them since SelectionDAG and IR types don't include them.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D133808/new/
https://reviews.llvm.org/D133808
More information about the llvm-commits
mailing list