[PATCH] D130947: TableGen: Introduce generated getSubRegisterClass function

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/SIRegisterInfo.h:281
+  const TargetRegisterClass *
+  getRegClassForOperandReg(const MachineRegisterInfo &MRI,
+                           const MachineOperand &MO) const;
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foad wrote:
> Jus bikeshedding on the name: would `getRegClassForRegOperand` make more sense, or just `getRegClassForOperand`?
It's specifically getting the class of the virtual register in the operand, not the underlying register class implied by the instruction


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  https://reviews.llvm.org/D130947/new/

https://reviews.llvm.org/D130947