[PATCH] D130947: TableGen: Introduce generated getSubRegisterClass function

[Jay Foad via Phabricator via llvm-commits]

foad accepted this revision.
foad added a comment.
This revision is now accepted and ready to land.

LGTM, just nits inline.



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Comment at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:632
+  /// Return a register class that can be used for a subregister copy from/into
+  /// \p SuperRC at \p Idx.
+  virtual const TargetRegisterClass *
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"SubRegIdx".


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Comment at: llvm/lib/Target/AMDGPU/SIRegisterInfo.h:281
+  const TargetRegisterClass *
+  getRegClassForOperandReg(const MachineRegisterInfo &MRI,
+                           const MachineOperand &MO) const;
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Jus bikeshedding on the name: would `getRegClassForRegOperand` make more sense, or just `getRegClassForOperand`?


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https://reviews.llvm.org/D130947