[PATCH] D133169: [AMDGPU] Constrain src0 RC of 64 bit shift amount on gfx90a

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec added a comment.

One important thing to note: defining this single RC implodes AMDGPUGenRegisterInfo.inc from 7.6Mb to 93Mb and increases time to generate this file from 5s to 35s.

So maybe we do not need it after all and can live with just hazard recognizer w/a.


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  https://reviews.llvm.org/D133169/new/

https://reviews.llvm.org/D133169