[PATCH] D131260: [DAG] select Cond, -1, C --> or (sext Cond), C if Cond is MVT::i1

[ChenZheng via Phabricator via llvm-commits]

shchenz added inline comments.


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Comment at: llvm/test/CodeGen/PowerPC/signbit-shift.ll:142
+; CHECK-NEXT:    li 3, 42
+; CHECK-NEXT:    isellt 3, 3, 4
 ; CHECK-NEXT:    blr
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The changes in this file seem regressions, especially for this case, more instructions and more registers. Do we know why?


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https://reviews.llvm.org/D131260