[PATCH] D131260: [DAG] select Cond, -1, C --> or (sext Cond), C if Cond is MVT::i1

[Amaury SECHET via Phabricator via llvm-commits]

deadalnix added inline comments.


================
Comment at: llvm/test/CodeGen/PowerPC/signbit-shift.ll:142
+; CHECK-NEXT:    li 3, 42
+; CHECK-NEXT:    isellt 3, 3, 4
 ; CHECK-NEXT:    blr
----------------
shchenz wrote:
> The changes in this file seem regressions, especially for this case, more instructions and more registers. Do we know why?
Yes. The PowerPC backend request for select_cc instruction. The select_cc instruction is not turned into arythmetic the way regular select instructions are.

This patch changes how select -> arithmetic transformations are done, which enable more transform in general, but specifically on PowerPC, this cases problems because it causes either select_cc to not be generated due select -> arithmetic transformations, or, alternatively, if the promotion to select_cc is prioritized, then the cases where the arithmetic transform was beneficial are not done.

Do we have a good idea when select_cc -> arithmetic is beneficial? If we have something reasonable here, we can add the select_cc transforms and get these regression dealt with.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D131260/new/

https://reviews.llvm.org/D131260